1. Field of the Invention
This invention relates to a semiconductor device and a production method thereof. More particularly, this invention relates to a semiconductor device having a novel ROM cell array structure and a production method thereof.
2. Description of the Related Art
A flat cell structure that is simple in construction and can be fabricated easily has been used in the past as a NOR type memory cell of a mask ROM (MROM), as shown in FIGS. 7 and 8. A unit memory cell of the MROM having such a flat cell structure is generally referred to as a xe2x80x9csingle drain type memory cellxe2x80x9d. The unit memory cell comprises a MOS transistor that in turn comprises two bit lines 31 formed of two diffusion layers containing a high concentration impurity and adjacent to each other, and a word line 32 formed of a poly-silicon film and crossing the bit lines 31.
Such a memory cell is programmed by a low threshold voltage (Vth=0.5 V, for example) or a high threshold voltage higher than a power source voltage (Vth=5V and power source voltage Vdd=3 V, for example). The memory cell is connected to selection transistors QBTOP and QBBOT and constitutes a NOR type ROM array as shown in an equivalent circuit diagram of FIG. 9.
Generally, sub-micron channel MOSFETs employ an LDD (Lightly Doped Drain) structure in order to cope with degradation resulting from a short channel effect and hot carriers.
However, it is not so easy to apply this LDD structure to the memory cell having the flat cell structure described above for the following reasons. The LDD structure is fabricated by the steps of forming a gate electrode, forming a low concentration impurity diffusion layer with this gate electrode as a mask, forming further a side wall spacer on the gate electrode, and then forming a high concentration impurity diffusion layer using these gate electrode and side wall spacer as masks. In the flat cell structure, on the other hand, a high concentration impurity diffusion layer to serve as bit lines and source/drain regions are first formed and word lines are then so formed as to cross the high concentration impurity diffusion layer. Therefore, the low concentration impurity diffusion layer cannot be formed in self-alignment between the high concentration impurity diffusion layer and a region that is to function later as the channel.
If the low concentration impurity diffusion layer is formed in self-alignment with the high concentration impurity diffusion layer, a series of the following process steps are necessary in addition to the ordinary fabrication steps of:
{circle around (1)} forming an oxide film on the entire surface of a substrate and forming openings of those regions of this oxide film which are to function as the low concentration impurity diffusion layer and as the high concentration impurity diffusion layer;
{circle around (2)} implanting impurities at a low dose by using the oxide film as a mask;
{circle around (3)} depositing further an oxide film on the oxide film having the openings, and etching back this oxide film to form a side wall spacer in the openings;
{circle around (4)} implanting impurities at a high dose using this oxide film and the side wall spacer as the mask; and
{circle around (5)} etching and removing the oxide film and the side wall spacer used as the mask.
As the size of transistors has further been reduced to the size in the sub-micron order, the size of the high concentration impurity diffusion layer is also reduced, and the resistance of the high concentration impurity diffusion layer increases with this scale-down. This increase of the resistance results in the decrease of a driving current of the transistor constituting the cell, and delays the access time to the MROM.
A salicide technology has been employed ordinarily as means for lowering the resistance of the high concentration impurity diffusion layers to function as bit lines. However, the salicide technology that uses the word line as the mask cannot be applied easily to the memory cell having the flat cell structure described above because the word line crosses the bit line and the thickness of an insulating film to be formed on the bit line is equal to the thickness of an insulating film to be formed in regions other than the bit line region and the word line region.
Japanese Patent Laid-Open No. HEI 6(1994)-291284 proposes, as a NOR type memory cell of another MROM, a high density MROM shown in FIGS. 10(a) to (d).
This MROM has the following construction. Gate electrodes 42 are formed on a bulk Si substrate 40 in which high concentration impurity diffusion layers 41 are formed as bit lines. A silicon layer 43 is formed on the gate electrodes 42, and high concentration impurity diffusion layers 43a are formed in the silicon layer 43. The upper and lower high concentration impurity diffusion layers 41 and 43a are connected to one another at contact portions 44, in consequence, a high integration density is achieved by using in common the gate electrodes 42. In other words, the high integration density is achieved by combining each MROM having the flat cell structure with each MROM having the inverted flat cell structure in such a manner as to share the gate electrode 42 between them.
Nonetheless, the MROM having this construction cannot cope with the short channel effect and lowering of the resistance of the high concentration impurity diffusion layer resulting from scale-down.
The present invention provides a semiconductor device comprising an insulating film, a plurality of word lines parallel to one another, a gate insulating film and a first conductivity type semiconductor layer that are formed in this order: wherein the surface of said insulating film is rendered flat with respect to the surface of said word lines, and said first conductivity type semiconductor layer includes bit lines comprising a plurality of second conductivity type high concentration impurity diffusion layers crossing said word lines and parallel to one another.
In another aspect, the present invention provides a method of producing a semiconductor device comprising the steps of: (a) forming an insulating film and word lines, and flattening the surface of said insulating film with respect to the surface of said word lines; (b) forming a gate insulating film and a first conductivity type semiconductor layer on said insulating film and said word lines; (c) forming a plurality of line-like insulating films parallel to one another and crossing said word lines, on said semiconductor layer; (d) implanting a second conductivity type impurity into said semiconductor layer with said line-like insulating film as a mask, and thereby forming a plurality of second conductivity type low concentration impurity diffusion layers; (e) forming an insulating side wall spacer on said line-like insulating film, and implanting a second conductivity type impurity into said semiconductor layer with said line-like insulating film and said side wall spacer as masks, and thereby forming a plurality of second conductivity type high concentration impurity diffusion layers; (f) forming a salicide film on the surface of said second conductivity type high concentration impurity diffusion layer with said line-like insulating film and said side wall spacer as masks; and (g) forming an inter-layer insulating film on said semiconductor layer inclusive of said line-like insulating film and said side wall spacer.
In still another aspect, the present invention provides a method of producing a semiconductor device which comprises an insulating film, a plurality of word lines parallel to one another, a gate insulating film and a first conductivity type semiconductor layer that are formed in this order: wherein the surface of said insulating film is rendered flat with respect to the surface of said word lines, and said first conductivity type semiconductor layer includes bit lines comprising a plurality of second conductivity type high concentration impurity diffusion layers crossing said word lines and parallel to one another comprising the steps of: (a) forming an insulating film and word lines, and flattening the surface of said insulating film with respect to the surface of said word lines; (b) forming a gate insulating film and a first conductivity type semiconductor layer on said insulating film and said word lines; (c) forming a plurality of line-like insulating films parallel to one another and crossing said word lines, on said semiconductor layer; (d) implanting a second conductivity type impurity into said semiconductor layer with said line-like insulating film as a mask, and thereby forming a plurality of second conductivity type high concentration impurity diffusion layers.